1. Field of the Invention
The present invention relates to an electrically programmable nonvolatile memory, for example, a flash electrically erasable programmable read only memory (EEPROM) or other semiconductor nonvolatile memory.
2. Description of the Related Art
Flash EEPROMs for judging the "1" or "0" state of data caused by injection of electrons in floating gates, for example, have conventionally been classified into the ordinary NOR type, divided bit-line NOR (DINOR) type, NAND type, etc.
In such a NOR type, DINOR type, and NAND type flash EEPROM, a write operation is performed by injecting channel hot electrons (CHE) into a floating gate, while the erase operation is performed by draining the electrons from the floating gate to the source by the Fowler-Nordheim (FN) tunnelling. A method has been proposed for erasing sectors of individual word lines as block units.
FIG. 1 is a circuit diagram showing the bias conditions at the time of word line sector erasure in a NOR type flash EEPROM of the related art.
In FIG. 1, WL.sub.1 to WL.sub.3 are word lines, BLS.sub.1 to BLS.sub.3 and BLD.sub.1 to BLD.sub.3 are bit lines, and MT.sub.11 to MT.sub.33 are memory cell transistors.
When performing word line sector erasure in a NOR type flash EEPROM, as shown in FIG. 1, the selected word line WL.sub.2 is set to -10 V, the nonselected word lines WL.sub.1 and WL.sub.3 are set to 0 V, the bit lines BLS.sub.1 to BLS.sub.3 serving as the common source lines are set to 6 V, the bit lines BLD.sub.1 to BLD.sub.3 of the drain side are set to a floating level, and the electrons in the floating gate FG of the memory cell transistor MT.sub.22 are drained.
FIG. 2 is a circuit diagram showing the bias conditions at the time of word line sector erasure in a DINOR type flash EEPROM of the related art.
In FIG. 2, SL.sub.11 to SL.sub.21 are selection gate lines, WL.sub.11 to WL.sub.18 and WL.sub.21 to WL.sub.28 are word lines, MBL.sub.11 and MBL.sub.12 are main bit lines, SBL.sub.11, SBL.sub.12, SBL.sub.21, and SBL.sub.22 are sub-bit lines, SRL.sub.11, SRL.sub.12, SRL.sub.21, and SRL.sub.22 are common source lines, ST.sub.11, ST.sub.12, ST.sub.21, and ST.sub.22 are selection gate transistors, and MT.sub.111 to MT.sub.118, MT.sub.121 to MT.sub.128, MT.sub.211 to MT.sub.218, and MT.sub.221 to MT.sub.228 are memory cell transistors.
When performing word line sector erasure in a DINOR type flash EEPROM, as shown in FIG. 2, the selection gate lines SL.sub.11 and SL.sub.21 are set to 0 V, the selected word lines WL.sub.11 to WL.sub.18 are set to 15 V, the nonselected word lines WL.sub.21 to WL.sub.28 are set to 0 V, the main bit lines MBL.sub.11 and MBL.sub.12 are set to a floating level, and the common source lines SRL.sub.11, SRL.sub.12, SRL.sub.21, and SRL.sub.22 are set to -6 V. Electrons are injected into the floating gates of the memory cell transistors MT.sub.111 to MT.sub.118 and MT.sub.121 to MT.sub.128.
FIG. 3 is a circuit diagram showing the bias conditions at the time of word line sector erasure in a NAND type flash EEPROM of the related art.
In FIG. 3, SL.sub.11, SL.sub.12, SL.sub.21, and SL.sub.22 are selection gate lines, WL.sub.11 to WL.sub.18, and WL.sub.21 to WL.sub.28 are word lines, BL.sub.11 and BL.sub.12 are bit lines, ST.sub.111, ST.sub.112, ST.sub.121, ST.sub.122, ST.sub.211, ST.sub.212, ST.sub.221, and ST.sub.222 are selection gate transistors, and MT.sub.111 to MT.sub.118, MT.sub.121 to MT.sub.128, MT.sub.211 to MT.sub.218, and MT.sub.221 to MT.sub.228 are memory cell transistors.
When performing word line sector erasure in a NAND type flash EEPROM, as shown in FIG. 3, the selection gate lines SL.sub.11, SL.sub.12, SL.sub.21, and SL.sub.22 are set to 0 V, the selected word lines WL.sub.11 to WL.sub.18 are set to -15 V, the nonselected word lines WL.sub.21 to WL.sub.28 are set to 0 V, the bit lines BL.sub.11 and BL.sub.12 are set to a floating level, and the substrate is set to 6 V. The electrons in the floating gates connected to the selected word lines are drained.
In such flash EEPROMs able to perform word line sector erasure, it is possible to perform rewriting and erasure in the very advantageous so-called "page mode".
Flash EEPROMs are able to perform such word line sector erasure, however, suffer from several problems.
That is, if performing rewriting or erase operations on only a specific word line in the overall memory, the cumulative number of cycles of rewriting and erasure of the word line will reach a certain guaranteed limit before that of the other word lines. That is, the life of the memory as a whole will be determined by the sector of a specific word line which is used most extensively even if the cumulative numbers of cycles of the majority of the word lines remain low.
FIG. 4 is a circuit diagram showing other bias conditions at the time of a write operation in a NOR type flash EEPROM of the related art. Note that the configuration of the circuit is basically the same as that of FIG. 1.
In FIG. 4, WL.sub.1, WL.sub.2, and WL.sub.3 are word lines, BLS.sub.1 to BLS.sub.3 are bit lines serving as common source lines, BLD.sub.1, BLD.sub.2, and BLD.sub.3 are bit lines, MT.sub.11 to MT.sub.33 are memory cell transistors, CG is a control gate, and FG is a floating gate.
When performing an erase operation in this memory array, while not shown, the selected word line WL.sub.2 is set to -10 V, the nonselected word lines WL.sub.1 and WL.sub.3 are set to 0 V, the common source lines BLS.sub.1 to BLS.sub.3 are set to 6 V, the bit lines BLD.sub.1, BLD.sub.2, and BLD.sub.3 are set to a floating level, and the electrons in the floating gates of the memory cell transistors connected to the selected word line WL.sub.2 are drained. Due to this, the threshold voltage V.sub.TH , of the erased memory cell transistors becomes 1 to 2 V or so.
At the time of a write operation, as shown in FIG. 4, the selected word line, for example, WL.sub.2, is set to 12 V, the nonselected word lines WL.sub.1 and WL.sub.3 are set to 0 V, the common source lines BLS.sub.1 to BLS.sub.3 are set to the ground level (0 V), the selected bit line BLD.sub.3 is set to 7 V, the nonselected bit lines BLD.sub.1 and BLD.sub.3 are set to 0 V, and channel hot electrons are injected into the floating gate FG of the selected memory transistor MT.sub.22.
Due to this, the threshold voltage V.sub.TH of the selected memory transistor MT.sub.22 becomes at least 5 V.
In the above-mentioned memory array, however, the data of the nonselected memory cell transistors MT.sub.12 and MT.sub.32 connected to the selected bit line BLD.sub.2 end up being destroyed by so-called drain disturbance phenomena.
There are two types of drain disturbance phenomena.
The first type of drain disturbance is one which occurs in a nonselected memory cell in which the data "1"(threshold voltage V.sub.TH &gt;5 V) is stored. The second type of drain disturbance is one which occurs in a nonselected memory cell of the data "0"(threshold voltage V.sub.TH = 1 to 2 V).
The phenomena of drain disturbance will be explained in more detail with reference to the configuration of FIG. 4 as an example.
Suppose that the data "1" and "0" correspond to the "high"(&gt;5 V) and "low"(=1 to 2 V) states of the threshold voltage and take note of the memory cell transistor MT.sub.22 of FIG. 4. At this time, assuming that the data stored in the memory cell transistors MT.sub.12 and MT.sub.32 other than the memory cell transistor MT.sub.22 connected to the same bit line BLD.sub.2 are all "1", when writing data in the memory cell transistor MT.sub.12 or MT.sub.32, the electrons built up in the floating gate FG of the memory cell transistor MT.sub.22 are drained or a hole is injected into the floating gate FG of the memory cell transistor MT.sub.22.
Accordingly, when the data stored in the memory cell transistor MT.sub.22 is "1", the storage electrons are lost and the threshold voltage V.sub.TH changes to 5 V or more. Despite this, data is written into the nonselected memory cell transistor MT.sub.12 or MT.sub.32, so the data stored there ends up being lost.
Further, when the stored data is "0", conversely avalanche hot holes are injected and the threshold voltage V.sub.TH is a low 1 to 2 V. Despite this, the voltage further falls. The threshold voltage sometimes falls too much and becomes negative. In such a case, it becomes impossible to correctly read any of the memory cell transistors MT.sub.22, MT.sub.12, and MT.sub.32 connected to the bit line BLD.sub.2, regardless of the selection of the cells, since a current flows in the bit line BLD.sub.2 at the time of the read operation.
The drain disturbance voltage may be supplied to the memory cell transistors other than the selected memory cell transistor connected to the same bit line a maximum of (N-1) times assuming the number of word lines to be N.
That is, when the stored data of all memory cell transistors other than the selected memory cell transistor connected to the same bit line are "1" then the drain disturbance voltage is applied (N-1) number of times.
Further, in a read only mask ROM, when writing stored data in the manufacturing process, the threshold voltages of the memory cells are made "high" or "low" in accordance with the data "1" or "0" to be stored.
For example, if the memory cells are N-channel MOS transistors, the data is written by injecting ions of a P-type impurity such as boron selectively in the memory cell transistors supposed to store the data "1".
When the data is all "1", a mask is prepared for injecting ions to all the memory cells. This entails preparing data so that the openings in the ion injection mask correspond to the positions where the data "1" is to be written, normally by computer, and fabricating the mask based on this data. In a word, the processing time becomes longer the greater the amount of data.